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| Datasheet File OCR Text: |
| - 1 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 1 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 features ? ? single ? 5v ? to ? 21v ? application ? ? wide ? input ? voltage ? range ? from ? 1.0v ? to ? 21v ? with ? external ? vcc ? ? ? output ? voltage ? range: ? 0.5v ? to ? 0.86* ? vin ? ? enhanced ? line/load ? regulation ? with ? feed \ forward ? ? programmable ? switching ? frequency ? up ? to ? 1.5mhz ? ? internal ? digital ? soft \ start/soft \ stop ? ? enable ? input ? with ? voltage ? monitoring ? capability ? ? thermally ? compensated ? current ? limit ? with ? robust ? hiccup ? mode ? over ? current ? protection ? ? smart ? internal ? ldo ? to ? improve ? light ? load ? and ? full ? load ? efficiency ?? ? external ? synchronization ? with ? smooth ? clocking ? ? ? enhanced ? pre \ bias ? start \ up ? ? precision ? reference ? voltage ? (0.5v+/ \ 0.5%) ? with ? margining ? capability ? ? vp ? for ? tracking ? applications ? (source/sink ? capability ? 16a) ? ? integrated ? mosfet ? drivers ? and ? bootstrap ? diode ? ? thermal ? shut ? down ? ? programmable ? power ? good ? output ? with ? tracking ? capability ? ? monotonic ? start \ up ? ? operating ? temp: ?\ 40 o c ?? < ? tj ? < ? 125 o c ?? ? small ? size: ? 5mm ? x ? 6mm ? pqfn ? ? lead \ free, ? halogen \ free ? and ? rohs ? compliant ? basic ? application ? ? ? figure ? 1: ? ir3895 ? basic ? application ? circuit ? description ? the ? ir3895 ? supirbuck tm ? is ? an ? easy \ to \ use, ? fully ? integrated ? and ? highly ? efficient ? dc/dc ? regulator. ?? the ? onboard ? pwm ? controller ? and ? mosfets ? make ? ir3895 ? a ? space \ efficient ? solution, ? providing ? accurate ? power ? delivery. ? ir3895 ? is ? a ? versatile ? regulator ? which ? offers ? programmable ? of ? switching ? frequency ? and ? the ? fixed ? internal ? current ? limit ? while ? operates ? in ? wide ? input ? and ? output ? voltage ? range. ? the ? switching ? frequency ? is ? programmable ? from ? 300khz ? to ? 1.5mhz ? for ? an ? optimum ? solution. ?? it ? also ? features ? important ? protection ? functions, ? such ? as ? pre \ bias ? startup, ? thermally ? compensated ? current ? limit, ? over ? voltage ? protection ? and ? thermal ? shutdown ? to ? give ? required ? system ? level ? security ? in ? the ? event ? of ? fault ? conditions. ? applications ? ? netcom ? applications ? ? embedded ? telecom ? systems ? ? server ? applications ? ? storage ? applications ? ? distributed ? point ? of ? load ? power ? architectures ? ? ? ? ? ? ? ? ? ? ? ? figure ? 2:ir3895 ? efficiency
- 2 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 2 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 ? ordering ? information ? ?? ir3895 ?D ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ??????? ? ? ? package tape ? & ? reel ? qty ? part ? number m ? 750 ? ir3895mtr1pbf ? m ? 4000 ? ir3895mtrpbf ? pin ? diagram ? 5m ? x ? 6mm ? power ? qfn ? (top ? view) ? pbf ? ? ? lead ? free ? tr/tr1 ? ? ? tape ? and ? reel ? m ? ? ? package ? type ? - 30 / 2/ ja jpcb cw cw ? ? ? ? ?? fb vref comp gnd rt/syncs_ctrl pgood - 3 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 3 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 block ? diagram ? ? gate drive logic + - soft start + control logic fault vcc vp fb rt/sync boot sw pgnd pvin enable e/ a vcc vcc/ ldo_out fault control uvcc uven fault fault pgood oc thermal shut down tsd hdin comp ldin intl_ss uvcc uven vref + hdrv ldrv vin + - v ldo_ref ldo vref ssok 0.5v fb vref vp por por por por uvcc por gnd zero crossing comparator dcm dcm vsns oc s_ctrl over voltage protection ov vref ov ov vin rff over current protection vp 0.15v ? ? figure ? 3: ? ir3895 ? simplified ? block ? diagram ? - 4 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 4 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 pin ? descriptions ? pin # pin name pin description 1 ? fb ? inverting ? input ? to ? the ? error ? amplifier. ? this ? pin ? is ? connected ? directly ? to ? the ? output ? of ? the ? regulator ? via ? resistor ? divider ? to ? set ? the ? output ? voltage ? and ? provide ? feedback ? to ? the ? error ? amplifier. ? 2 ? vref ? internal ? reference ? voltage, ? it ? can ? be ? used ? for ? margining ? operation ? also. ? in ? normal ? and ? sequencing ? mode ? operation, ? vref ? is ? left ? floating. ? a ? 1nf ? ceramic ? capacitor ? is ? recommended ? between ? this ? pin ? and ? gnd. ?? in ? tracking ? mode ? operation, ? vref ? should ? be ? tied ? to ? gnd. ? 3 ? comp ? output ? of ? error ? amplifier. ? an ? external ? resistor ? and ? capacitor ? network ? is ? typically ? connected ? from ? this ? pin ? to ? fb ? to ? provide ? loop ? compensation. ? 4 ? gnd ? signal ? ground ? for ? internal ? reference ? and ? control ? circuitry. ? 5 ? rt/sync ? multi \ function ? pin ? to ? set ? switching ? frequency. ? use ? an ? external ? resistor ? from ? this ? pin ? to ? gnd ? to ? set ? the ? free \ running ? switching ? frequency. ? an ? external ? clock ? signal ? can ? be ? connected ? to ? this ? pin ? through ? a ? diode ? so ? that ? the ? device?s ? switching ? frequency ? is ? synchronized ? with ? the ? external ? clock. ? 6 ? s_ctrl ? soft ? start/stop ? control. ? a ? high ? logic ? input ? enables ? the ? device ? to ? go ? into ? the ? internal ? soft ? start; ? a ? low ? logic ? input ? enables ? the ? output ? soft ? discharged. ? pull ? this ? pin ? to ? vcc ? if ? this ? function ? is ? not ? used. ? 7 ? pgood ? power ? good ? status ? pin. ? output ? is ? open ? drain. ? connect ? a ? pull ? up ? resistor ? from ? this ? pin ? to ? the ? voltage ? lower ? than ? or ? equal ? to ? the ? vcc. ? 8 ? vsns ? sense ? pin ? for ? over \ voltage ? protection ? and ? pgood. ? it ? is ? optional ? to ? tie ? this ? pin ? to ? fb ? pin ? directly ? instead ? of ? using ? a ? resistor ? divider ? from ? vout. ? 9 ? vin ? input ? voltage ? for ? internal ? ldo. ? a ? 1.0f ? capacitor ? should ? be ? connected ? between ? this ? pin ? and ? pgnd. ? if ? external ? supply ? is ? connected ? to ? vcc/ldo_out ? pin, ? this ? pin ? should ? be ? shorted ? to ? vcc/ldo_out ? pin. ? 10 ? vcc/ldo_out ? input ? bias ? for ? external ? vcc ? voltage/ ? output ? of ? internal ? ldo. ? place ? a ? minimum ? 2.2f ? cap ? from ? this ? pin ? to ? pgnd. ? 11 ? pgnd ? power ? ground. ? this ? pin ? serves ? as ? a ? separated ? ground ? for ? the ? mosfet ? drivers ? and ? should ? be ? connected ? to ? the ? system?s ? power ? ground ? plane. ? 12 ? sw ? switch ? node. ? this ? pin ? is ? connected ? to ? the ? output ? inductor. ? 13 ? pvin ? input ? voltage ? for ? power ? stage. ? 14 ? boot ? supply ? voltage ? for ? high ? side ? driver, ? a ? 100nf ? capacitor ? should ? be ? connected ? between ? this ? pin ? and ? sw ? pin. ? 15 ? enable ? enable ? pin ? to ? turn ? on ? and ? off ? the ? device, ? if ? this ? pin ? is ? connected ? to ? pvin ? pin ? through ? a ? resistor ? divider, ? input ? voltage ? uvlo ? can ? be ? implemented. ? 16 ? vp ? input ? to ? error ? amplifier ? for ? tracking ? purposes. ? in ? the ? normal ? operation, ? it ? is ? left ? floating ? and ? no ? external ? capacitor ? is ? required. ? in ? the ? sequencing ? or ? the ? tracking ? mode ? operation, ? an ? external ? signal ? can ? be ? applied ? as ? the ? reference. ? 17 ? gnd ? signal ? ground ? for ? internal ? reference ? and ? control ? circuitry. ? ?? ? - 5 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 5 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 absolute ? maximum ? ratings ? ? stresses ? beyond ? those ? listed ? under ? ?absolute ? maximum ? ratings? ? may ? cause ? permanent ? damage ? to ? the ? device. ? these ? are ? stress ? ratings ? only ? and ? functional ? operation ? of ? the ? device ? at ? these ? or ? any ? other ? conditions ? beyond ? those ? indicated ? in ? the ? operational ? sections ? of ? the ? specifications ? are ? not ? implied. ? ? pvin, ? vin ? \ 0.3v ?? to ?? 25v ? vcc/ldo_out ?\ 0.3v ?? to ?? 8v ? (note ? 2) ? boot ? \ 0.3v ?? to ?? 33v ? sw ?\ 0.3v ?? to ?? 25v ? (dc), ?\ 4v ? to ? 25v ? (ac, ? 100ns) ? boot ? to ? sw ? \ 0.3v ?? to ?? vcc ? + ? 0.3v ? (note ? 1) ? s_ctrl, ? pgood ?\ 0.3v ?? to ?? vcc ? + ? 0.3v ? (note ? 1) ? other ? input/output ? pins ? \ 0.3v ?? to ?? +3.9v ? pgnd ? to ? gnd ?\ 0.3v ?? to ?? +0.3v ? storage ? temperature ? range ? \ 55c ?? to ?? 150c ? junction ? temperature ? range ?\ 40c ?? to ?? 150c ? (note ? 2) ? esd ? classification ? (hbm ? jesd22 \ a114) ? 2kv ? moisture ? sensitivity ? level ? jedec ? level ? 3@260c ?? ? note ? 1: ? must ? not ? exceed ? 8v ? note ? 2: ? vcc ? must ? not ? exceed ? 7.5v ? for ? junction ? temperature ? between ?\ 10c ? and ?\ 40c ? ? ? - 6 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 6 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 electrical ? specifications ? recommended ? operating ? conditions ? for ? reliable ? operation ? with ? margin ? ? symbol ? min ? max ? units input ? voltage ? range* ? pvin ? 1.0 ? 21 ? v ? ?? input ? voltage ? range** ? vin ? 6.8 ? 21 ? supply ? voltage ? range*** ? v cc ? 4.5 ? 7.5 ? supply ? voltage ? range ? boot ? to ? sw ? 4.5 ? 7.5 ? output ? voltage ? range ? v o ? 0.5 ? 0.86xvin ? output ? current ? range ? i o ? 0 ? 16 ? a ? switching ? frequency ? f s ? 300 ? 1500 ? khz ? operating ? junction ? temperature ? t j ?\ 40 ? 125 ? c ? *maximum ? sw ? node ? voltage ? should ? not ? exceed ? 25v. ? **for ? internally ? biased ? single ? rail ? operation. ?? *** ? vcc/ldo_out ? can ? be ? connected ? to ? an ? external ? regulated ? supply. ? if ? so, ? the ? vin ? input ? should ? be ? connected ? to ? vcc/ldo_out ? pin. ? electrical ? characteristics ? unless ? otherwise ? specified, ? these ? specifications ? apply ? over, ? 6.8v ? < ? vin ? = ? pvin ? < ? 21v, ? vref ? = ? 0.5v ? in ? 0c ? < ? t j ? < ? 125c. ?? typical ? values ? are ? specified ? at ? t a ? = ? 25c. ? parameter ? symbol ? conditions ? min ? typ ? max ? unit ? power ? stage ? power ? losses ? p loss ? vin ? = ? 12v, ? v o ? = ? 1.2v, ? i o ? = ? 16a, ?? fs ? = ? 600khz, ? l ? = ? 0.4uh, ?? vcc ? = ? 6.4v ? (internal ? ldo), ? note ? 4 ? ?? 3.4 ??? w ? top ? switch ? r ds(on)_top ? vboot ?\? vsw= ? 6.4v, ? i o ? = ? 16a, ? t j ? =25c ?? 9.6 ? 13.5 ? m ?? bottom ? switch ? r ds(on)_bot ? vcc ? = ? 6.4v, ? i o ? = ? 16a, ? t j ? =25c ??? 4.2 ? 6.1 ?? bootstrap ? diode ? forward ? voltage ? ?? i(boot) ? = ? 15ma ? 200 ? 300 ? 500 ? mv ? sw ? leakage ? current ? i sw ? sw ? = ? 0v, ? enable ? = ? 0v ????? 1 ? a ? sw ? = ? 0v, ? enable ? = ? high, ? vp ? = ? 0v ??? dead ? band ? time ? t db ? note ? 4 ?? 20 ?? ns ? supply ? current ? vin ? supply ? current ? (standby) ? i in(standby) ? en ? = ? low, ? no ? switching ????? 100 ? a ? vin ? supply ? current ? (dynamic) ? i in(dyn) ? en ? = ? high, ? fs ? = ? 600khz, ?? vin ? = ? pvin ? = ? 21v ? ?? 20 ? 23 ? ma ? vcc ? ldo ? output ? output ? voltage ? v cc ? ? vin(min) ? = ? 6.8v, ? icc ? = ? 0 \ 50ma, ? cload ? = ? 2.2uf, ? dcm ? = ? 0 ? 6.0 ? 6.4 ? 6.7 ? v ? ? vin(min) ? = ? 6.8v, ? icc ? = ? 0 \ 50ma, ? cload ? = ? 2.2uf, ? dcm ? = ? 1 ? 4.0 ? 4.4 ? 4.85 ? vcc ? dropout ? v cc_drop ?? icc=50ma,cload=2.2uf ??? 0.8 ? v ? short ? circuit ? current ? ishort ?? ? 70 ?? ma ? - 7 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 7 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? zero \ crossing ? comparator ? delay ? tdly_zc ? note ? 4 ?? 256/fs ?? s ? zero \ crossing ? comparator ? offset ? vos_zc ? note ? 4 ?\ 4 ? 0 ? 4 ? mv ? oscillator ? rt ? voltage ? vrt ??? ?? 1.0 ?? ?? v ? frequency ? range ? f s ? rt ? = ? 80.6k ? 270 ? 300 ? 330 ? khz ? rt ? = ? 39.2k ? 540 ? 600 ? 660 ? rt ? = ? 15.0k ? 1350 ? 1500 ? 1650 ? ramp ? amplitude ? vramp ? vin ? = ? 6.8v, ? vin ? slew ? rate ? max ? = ? 1v/s, ? note ? 4 ? ? 1.02 ?? vp \ p ? vin ? = ? 12v, ? vin ? slew ? rate ? max ? = ? 1v/s, ? note ? 4 ? ? 1.80 ?? vin ? = ? 21v, ? vin ? slew ? rate ? max ? = ? 1v/s, ? note ? 4 ? ? 3.15 ?? vcc=vin=5v,for ? external ? vcc ? operation, ? note ? 4 ? ? 0.75 ?? ramp ? offset ? ramp(os) ? note ? 4 ?? 0.16 ?? v ? min ? pulse ? width ? tmin(ctrl) ? note ? 4 ??? 60 ? ns ? max ? duty ? cycle ? dmax ? fs ? = ? 300khz, ? pvin ? = ? vin ? = ? 12v ? 86 ?? ? % ? fixed ? off ? time ? toff ? note ? 4 ?? 200 ? 250 ? ns ? sync ? frequency ? range ? fsync ?? 270 ?? 1650 ? khz ? sync ? pulse ? duration ? tsync ?? 100 ? 200 ?? ns ? sync ? level ? threshold ? high ?? ? 3 ?? ? v ? low ?? ? ? 0.6 ? error ? amplifier ? input ? offset ? voltage ? vos_vref ? vfb ? ? ? vref, ? vref ? = ? 0.5v ?\ 1.5 ??? +1.5 ? % ? vos_vp ? vfb ? ? ? vp, ? vp ? = ? 0.5v,vref=0 ?\ 1.5 ?? +1.5 ? input ? bias ? current ? ifb(e/a) ?? \ 1 ?? +1 ? a ? input ? bias ? current ? ivp(e/a) ?? 0 ?? +4 ? sink ? current ? isink(e/a) ?? 0.4 ? 0.85 ? 1.2 ? ma ? source ? current ? isource(e/a) ?? 4 ? 7.5 ? 11 ? ma ? slew ? rate ? sr ? note ? 4 ? 7 ? 12 ? 20 ? v/s ? gain \ bandwidth ? product ? gbwp ? note ? 4 ? 20 ? 30 ? 40 ? mhz ? dc ? gain ? gain ? note ? 4 ? 100 ? 110 ? 120 ? db ? maximum ? output ? voltage ? vmax(e/a) ?? 1.7 ? 2.0 ? 2.3 ? v ? minimum ? output ? voltage ? vmin(e/a) ?? ? ? 100 ? mv ? common ? mode ? input ? voltage ? ? ? 0 ?? 1.2 ? v ? reference ? voltage ? feedback ? voltage ? vfb ? vref ? and ? vp ? pin ? floating ?? 0.5 ??? v ? - 8 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 8 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? accuracy ?? 0c ? < ? tj ? < ? 70c ?\ 0.5 ?? +0.5 ? % ? ?\ 40c ? < ? tj ? < ? 125c, ? note ? 3 ?\ 1.0 ?? +1.0 ? vref ? margining ? voltage ? ? vref_marg ?? 0.4 ?? 1.2 ? v ? sink ? current ? isink_vref ? vref ? = ? 0.6v ? 12.7 ? 16.0 ? 19.3 ? a ? source ? current ? isrc_vref ? vref ? = ? 0.4v ? 12.7 ? 16.0 ? 19.3 ? vref ? comparator ? threshold ? vref_disable ? vref ? pin ? connected ? externally ??? 0.15 ? v ? vref_enable ? 0.4 ?? ? soft ? start/stop ? soft ? start ? ramp ? rate ? ramp ? (ss_start) ? ? 0.16 ? 0.2 ? 0.24 ? mv/s ? soft ? start ? ramp ? rate ? ramp ? (ss_stop) ? ?\ 0.24 ?\ 0.2 ?\ 0.16 ? s_ctrl ? threshold ? high ?? 2.4 ?? ? v ? low ?? ? ? 0.6 ? power ? good ? pgood ? turn ? on ? threshold ? vpg(on) ? vsns ? rising, ? 0.4v ? < ? vref ? < ? 1.2v ?? 85 ? 90 ?? 95 ? % ? vref ? vsns ? rising, ? vref ? < ? 0.1v ? 85 ? 90 ? 95 ? % ? vp ? pgood ? lower ? turn ? off ? threshold ? vpg(lower) ? vsns ? falling, ? 0.4v ? < ? vref ? < ? 1.2v ? 80 ?? 85 ? 90 ?? % ? vref ? vsns ? falling, ? vref ? < ? 0.1v ? 80 ? 85 ? 90 ? % ? vp ? pgood ? turn ? on ? delay ? vpg(on)_dly ? vsns ? rising, ? see ? vpg(on) ??? 1.28 ??? ms ? pgood ? upper ? turn ? off ? threshold ? vpg(upper) ? vsns ? rising, ? 0.4v ? < ? vref ? < ? 1.2v ?? 115 ? 120 ? 125 ?? % ? vref ? vsns ? rising, ? vref ? < ? 0.1v ? 115 ? 120 ? 125 ? % ? vp ? pgood ? comparator ? delay ? vpg(comp)_ dly ? vsns ? < ? vpg(lower) ? or ?? vsns ? > ? vpg(upper) ? 1 ? 2 ? 3.5 ? s ? pgood ? voltage ? low ? pg(voltage) ? ipgood ? = ?\ 5ma ????? 0.5 ?? v ? tracker ? comparator ? upper ? threshold ? vpg(tracker _upper) ? vp ? rising, ? vref ? < ? 0.1v ??? 0.4 ??? v ? tracker ? comparator ? lower ? threshold ? vpg(tracker _lower) ? vp ? falling, ? vref ? < ? 0.1v ??? 0.3 ??? tracker ? comparator ? delay ? tdelay(track er) ? vp ? rising, ? vref ? < ? 0.1v,see ? vpg(tracker_upper) ? ?? 1.28 ??? ms ? under \ voltage ? lockout ? vcc \ start ? threshold ? v cc _uvlo_ ? start ? vcc ? rising ? trip ? level ? 4.0 ? 4.2 ? 4.4 ? v ? vcc \ stop ? threshold ? v cc _uvlo_ ? stop ? vcc ? falling ? trip ? level ? 3.7 ? 3.9 ? 4.1 ? enable \ start \ threshold ? enable_uvl o_start ? supply ? ramping ? up ? 1.14 ? 1.2 ? 1.26 ? v ? - 9 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 9 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? enable \ stop \ threshold ? enable_uvl o_stop ? supply ? ramping ? down ? 0.95 ? 1 ? 1.05 ? enable ? leakage ? current ? ien ? enable ? = ? 3.3v ???? 1 ? a ? over \ voltage ? protection ? ovp ? trip ? threshold ? ovp_vth ? vsns ? rising, ? 0.45v ? < ? vref ? < ? 1.2v ? 115 ?? 120 ? 125 ? % ? vref ? vsns ? rising, ? vref ? < ? 0.1v ? 115 ? 120 ? 125 ? % ? vp ? ovp ? comparator ? delay ? ovp_tdly ?? 1 ? 2 ? 3.5 ? s ? over \ current ? protection ? current ? limit ? i limit ? tj ? = ? 25c, ? vcc ? = ? 6.4v ? 18.0 ? 20.5 ? 24.4 ? a ? hiccup ? blanking ? time ? tblk_hiccup ??? ?? 20.48 ?? ms ? over \ temperature ? protection ? thermal ? shutdown ? threshold ? ttsd ? note ? 4 ? ? 145 ? ? ? c ? hysteresis ? ttsd_hys ? note ? 4 ??? 20 ?? ? note ? 3: ? cold ? temperature ? performance ? is ? guaranteed ? via ? correlation ? using ? statistical ? quality ? control. ? not ? tested ? in ? production. ? note ? 4: ? guaranteed ? by ? design ? but ? not ? tested ? in ? production. ? - 10 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 10 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? efficiency ? and ? power ? loss ? curves ? ? pvin ? = ? 12v, ? vcc ? = ? internal ? ldo ? (4.4v/6.4v), ? io ? = ? 0a \ 16a, ? fs ? = ? 600khz, ? room ? temperature, ? no ? air ? flow. ? note ? that ? the ? efficiency ? and ? power ? loss ? curves ? include ? the ? losses ? of ? ir3895, ? the ? inductor ? losses ? and ? the ? losses ? of ? the ? input ? and ? output ? capacitors. ? the ? table ? below ? shows ? the ? inductors ? used ? for ? each ? of ? the ? output ? voltages ? in ? the ? efficiency ? measurement. ? vout(v) ? lout(h) ? p/n ? dcr(m ) ? 1.0 ? 0.4 ? 59pr9875n ? (vitec) ? 0.29 ? 1.2 ? 0.4 ? 59pr9875n ? (vitec) ? 0.29 ? 1.8 ? 0.47 ? 7443330047(wurth ? elektronik) ? 0.8 ? 3.3 ? 0.82 ?? mpc1040lr88c(nec/tokin) ? 2.3 ? 5 ? 1.0 ? 7443330010(wurth ? elektronik) ? 1.35 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 11 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 11 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? efficiency ? and ? power ? loss ? curves ? ? pvin ? = ? 12v, ? vcc ? = ? external ? 5v, ? io ? = ? 0a \ 16a, ? fs ? = ? 600khz, ? room ? temperature, ? no ? air ? flow. ? note ? that ? the ? efficiency ? and ? power ? loss ? curves ? include ? the ? losses ? of ? ir3895, ? the ? inductor ? losses ? and ? the ? losses ? of ? the ? input ? and ? output ? capacitors. ? the ? table ? below ? shows ? the ? inductors ? used ? for ? each ? of ? the ? output ? voltages ? in ? the ? efficiency ? measurement. ? vout(v) ? lout(h) ? p/n ? dcr(m ) ? 1.0 ? 0.4 ? 59pr9875n ? (vitec) ? 0.29 ? 1.2 ? 0.4 ? 59pr9875n ? (vitec) ? 0.29 ? 1.8 ? 0.47 ? 7443330047(wurth ? elektronik) ? 0.8 ? 3.3 ? 0.82 ?? mpc1040lr88c(nec/tokin) ? 2.3 ? 5 ? 1.0 ? 7443330010(wurth ? elektronik) ? 1.35 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 12 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 12 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? efficiency ? and ? power ? loss ? curves ? ? pvin ? = ? 5.0v, ? vcc ? = ? 5.0v, ? io ? = ? 0a \ 16a, ? fs ? = ? 600khz, ? room ? temperature, ? no ? air ? flow. ? note ? that ? the ? efficiency ? and ? power ? loss ? curves ? include ? the ? losses ? of ? ir3895, ? the ? inductor ? losses ? and ? the ? losses ? of ? the ? input ? and ? output ? capacitors. ? the ? table ? below ? shows ? the ? inductors ? used ? for ? each ? of ? the ? output ? voltages ? in ? the ? efficiency ? measurement. ? vout(v) ? lout(h) ? p/n ? dcr(m ) ? 1.0 ? 0.3 ? 59pr9874n ? (vitec) ? 0.29 ? 1.2 ? 0.3 ? 59pr9874n ? (vitec) ? 0.29 ? 1.8 ? 0.4 ? 59pr9875n ? (vitec) ? 0.29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 13 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 13 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 thermal ? derating ? curves ? measurement ? done ? on ? evaluation ? board ? of ? irdc3895.pcb ? is ? 4 ? layer ? board ? with ? 2 ? oz ? copper, ? fr4 ? material, ? size ? 2.23"x2" ? pvin ? = ? 12v, ? vout=1.2v, ? vcc ? = ? internal ? ldo ? (6.4v), ? fs ? = ? 600khz ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pvin ? = ? 12v, ? vout=3.3v, ? vcc ? = ? internal ? ldo ? (6.4v), ? fs ? = ? 600khz ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 14 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 14 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 rdson ? of ? mosfets ? over ? temperature ? at ? v cc =6.4v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???????????? rdson ? of ? mosfets ? over ? temperature ? at ? vcc=5.0v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 15 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 15 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? characteristics ? ( \ 40c ? to ? +125c) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - 16 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 16 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? characteristics ? ( \ 40c ? to ? +125c) ? ? ??? ? ? ? ? ? ? ? note: ? see ? over ? current ? protection ? section ? ? ? ?????????? note: ? see ? over ? current ? protection ? section ? - 17 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 17 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 theory ? of ? operation ? ? description ? the ? ir3895 ? uses ? a ? pwm ? voltage ? mode ? control ? scheme ? with ? external ? compensation ? to ? provide ? good ? noise ? immunity ? and ? maximum ? flexibility ? in ? selecting ? inductor ? values ? and ? capacitor ? types. ?? the ? switching ? frequency ? is ? programmable ? from ? 300 ? khz ?? to ? 1.5mhz ? and ? provides ? the ? capability ? of ? optimizing ? the ? design ? in ? terms ? of ? size ? and ? performance. ? ir3895 ? provides ? precisely ? regulated ? output ? voltage ? programmed ? via ? two ? external ? resistors ? from ? 0.5v ? to ? 0.86*vin. ? the ? ir3895 ? operates ? with ? an ? internal ? bias ? supply ? (ldo) ? which ? is ? connected ? to ? the ? vcc/ldo_out ? pin. ? this ? allows ? operation ? with ? single ? supply. ? the ? bias ? voltage ? is ? variable ? according ? to ? load ? condition. ? if ? the ? output ? load ? current ? is ? less ? than ? half ? of ? the ? peak \ to \ peak ? inductor ? current, ? a ? lower ? bias ? voltage, ? 4.4v, ? is ? used ? as ? the ? internal ? gate ? drive ? voltage; ? otherwise, ? a ? higher ? voltage, ? 6.4v, ? is ? used. ?? this ? feature ? helps ? the ? converter ? to ? reduce ? power ? losses. ? the ? ic ? can ? also ? be ? operated ? with ? an ? external ? supply ? from ? 4.5 ? to ? 7.5v, ? allowing ? an ? extended ? operating ? input ? voltage ? (pvin) ? range ? from ? 1.0v ? to ? 21v. ? for ? using ? the ? internal ? ldo ? supply, ? the ? vin ? pin ? should ? be ? connected ? to ? pvin ? pin. ?? if ? an ? external ? supply ? is ? used, ? it ? should ? be ? connected ? to ? vcc/ldo_out ? pin ? and ? the ? vin ? pin ? should ? be ? shorted ? to ? vcc/ldo_out ? pin. ? the ? device ? utilizes ? the ? on \ resistance ? of ? the ? low ? side ? mosfet ? (sync ? fet) ? for ? over ? current ? protection. ? this ? method ? enhances ? the ? converter?s ? efficiency ? and ? reduces ? cost ? by ? eliminating ? the ? need ? for ? external ? current ? sense ? resistor. ? ir3895 ? includes ? two ? low ? r ds(on) ? mosfets ? using ? ir?s ? hexfet ? technology. ? these ? are ? specifically ? designed ? for ? high ? efficiency ? applications. ??? under \ voltage ? lockout ? and ? por ? the ? under \ voltage ? lockout ? circuit ? monitors ? the ? voltage ? of ? vcc/ldo_out ? pin ? and ? the ? enable ? input. ? it ? assures ? that ? the ? mosfet ? driver ? outputs ? remain ? in ? the ? off ? state ? whenever ? either ? of ? these ? two ? signals ? drop ? below ? the ? set ? thresholds. ? normal ? operation ? resumes ? once ? vcc/ldo_out ? and ? enable ? rise ? above ? their ? thresholds. ? the ? por ? (power ? on ? ready) ? signal ? is ? generated ? when ? all ? these ? signals ? reach ? the ? valid ? logic ? level ? (see ? system ? block ? diagram). ? when ? the ? por ? is ? asserted ? the ? soft ? start ? sequence ? starts ? (see ? soft ? start ? section). ? enable ? the ? enable ? features ? another ? level ? of ? flexibility ? for ? start ? up. ? the ? enable ? has ? precise ? threshold ? which ? is ? internally ? monitored ? by ? under \ voltage ? lockout ? (uvlo) ? circuit. ? therefore, ? the ? ir3895 ? will ? turn ? on ? only ? when ? the ? voltage ?? at ? the ? enable ? pin ? exceeds ? this ? threshold, ? typically, ? 1.2v. ? if ? the ? input ? to ? the ? enable ? pin ? is ? derived ? from ? the ? bus ? voltage ? by ? a ? suitably ? programmed ? resistive ? divider, ? it ? can ? be ? ensured ? that ? the ? ir3895 ? does ? not ? turn ? on ? until ? the ? bus ? voltage ? reaches ? the ? desired ? level ? (fig. ? 4). ? only ? after ? the ? bus ? voltage ? reaches ? or ? exceeds ? this ? level ? and ? voltage ? at ? the ? enable ? pin ? exceeds ? its ? threshold, ? ir3895 ? will ? be ? enabled. ? therefore, ? in ? addition ? to ? being ? a ? logic ? input ? pin ? to ? enable ? the ? ir3895, ? the ? enable ? feature, ? with ? its ? precise ? threshold, ? also ? allows ? the ? user ? to ? implement ? an ? under \ voltage ? lockout ? for ? the ? bus ? voltage ? (pvin). ? this ? is ? desirable ? particularly ? for ? high ? output ? voltage ? applications, ? where ? we ? might ? want ? the ? ir3895 ? to ? be ? disabled ? at ? least ? until ? pvin ? exceeds ? the ? desired ? output ? voltage ? level. ? pvin (12v) vcc enable intl_ss 10. 2 v enable threshold = 1.2v ? figure ? 4: ? normal ? start ? up, ? device ? turns ? on ?? when ? the ? bus ? voltage ? reaches ? 10.2v ? a ? resistor ? divider ? is ? used ? at ? en ? pin ? from ? pvin ? to ? turn ? on ? the ? device ? at ? 10.2v. ? ? - 18 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 18 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 pvin(12v) vcc intl_ss enable >1.2v vp>1v ? figure ? 5a: ? recommended ? startup ? for ? normal ? operation ? pvin (12v) vcc enable > 1. 2 v intl_ss vp ? figure ? 5b: ? recommended ? startup ? for ? sequencing ? operation ? (ratiometric ? or ? simultaneous) ?? pvin (12v) vcc enable > 1. 2 v intl_ss vp vref=0 ? figure ? 5c: ? recommended ? startup ? for ?? memory ? tracking ? operation ? (vtt \ ddr) ? figure ? 5a ? shows ? the ? recommended ? start \ up ? sequence ? for ? the ? normal ? (non \ tracking, ? non \ sequencing) ? operation ? of ? ir3895, ? when ? enable ? is ? used ? as ? a ? logic ? input. ? figure ? 5b ? shows ? the ? recommended ? startup ? sequence ? for ? sequenced ? operation ? of ? ir3895 ? with ? enable ? used ? as ? logic ? input. ? figure ? 5c ? shows ? the ? recommended ? startup ? sequence ? for ? tracking ? operation ? of ? ir3895 ? with ? enable ? used ? as ? logic ? input. ?? in ? normal ? and ? sequencing ? mode ? operation, ? vref ? is ? left ? floating. ? a ? 1nf ? ceramic ? capacitor ? is ? recommended ? between ? this ? pin ? and ? gnd. ?? in ? tracking ? mode ? operation, ? vref ? should ? be ? tied ? to ? gnd. ? it ? is ? recommended ? to ? apply ? the ? enable ? signal ? after ? the ? vcc ? voltage ? has ? been ? established. ? if ? the ? enable ? signal ? is ? present ? before ? vcc, ? a ? 50k ?? resistor ? can ? be ? used ? in ? series ? with ? the ? enable ? pin ? to ? limit ? the ? current ? flowing ? into ? the ? enable ? pin. ??? pre \ bias ? startup ? ir3895 ? is ? able ? to ? start ? up ? into ? pre \ charged ? output, ? which ? prevents ? oscillation ? and ? disturbances ? of ? the ? output ? voltage. ?? the ? output ? starts ? in ? asynchronous ? fashion ? and ? keeps ? the ? synchronous ? mosfet ? (sync ? fet) ? off ? until ? the ? first ? gate ? signal ? for ? control ? mosfet ? (ctrl ? fet) ? is ? generated. ? figure ? 6a ? shows ? a ? typical ? pre \ bias ? condition ? at ? start ? up. ? the ? sync ? fet ? always ? starts ? with ? a ? narrow ? pulse ? width ? (12.5% ? of ? a ? switching ? period) ? and ? gradually ? increases ? its ? duty ? cycle ? with ? a ? step ? of ? 12.5% ? until ? it ? reaches ? the ? steady ? state ? value. ? the ? number ? of ? these ? startup ? pulses ? for ? each ? step ? is ? 16 ? and ? it?s ? internally ? programmed. ? figure ? 6b ? shows ? the ? series ? of ? 16x8 ? startup ? pulses. ? vo [v] [time] pre-bias voltage ? figure ? 6a: ? pre \ bias ? startup ? ... ... ... hdrv ... ... ... 16 end of pb ldrv 12.5% 25% 87.5% 16 ... ... ... ... ? figure ? 6b: ? pre \ bias ? startup ? pulses ? - 19 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 19 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 soft \ start ? ir3895 ? has ? an ? internal ? digital ? soft \ start ? to ? control ? the ? output ? voltage ? rise ? and ? to ? limit ? the ? current ? surge ? at ? the ? start \ up. ? to ? ensure ? correct ? start \ up, ? the ? soft \ start ? sequence ? initiates ? when ? the ? enable ? and ? vcc ? rise ? above ? their ? uvlo ? thresholds ? and ? generate ? the ? power ? on ? ready ? (por) ? signal. ? the ? internal ? soft \ start ? (intl_ss) ? signal ? linearly ? rises ? with ? the ? rate ? of ? 0.2mv/s ? from ? 0v ? to ? 1.5v. ? figure ? 7 ? shows ? the ? waveforms ? during ? soft ? start ? (also ? refer ? to ? fig. ? 20). ? the ? normal ? vout ? start ? up ? time ? is ? fixed, ? and ? is ? equal ? to: ? ?? 0.65v-0.15v 2.5ms (1) 0.2mv/ s start t ? ? ? ?????????? during ? the ? soft ? start ? the ? over \ current ? protection ? (ocp) ? and ? over \ voltage ? protection ? (ovp) ? is ? enabled ? to ? protect ? the ? device ? for ? any ? short ? circuit ? or ? over ? voltage ? condition. ? por intl_ss vout 0.15v 0.65v t 1 t 2 t 3 1.5v 3.0v ? figure ? 7: ? theoretical ? operation ? waveforms ? during ?? soft \ start ? (non ? tracking ? / ? non ? sequencing) ? operating ? frequency ?? the ? switching ? frequency ? can ? be ? programmed ? between ?? 300 ? khz ? ? ? 1500 ? khz ? by ? connecting ? an ? external ? resistor ? from ? r t ? pin ? to ? gnd. ? table ? 1 ? tabulates ? the ? oscillator ? frequency ? versus ? r t . ? shutdown ? ir3895 ? can ? be ? shutdown ? by ? pulling ? the ? enable ? pin ? below ? its ? 1.0v ? threshold. ? this ? will ? tri \ state ? both ? the ? high ? side ? and ? the ? low ? side ? driver. ? ? ? ? t able ? 1: ? s witching ? f requency ? (f s ) ? vs . ? e xternal ? r esistor ? ( r t ) ? rt ? (k ? ) freq ? (khz) ? 80.6 300 ? 60.4 400 ? 48.7 500 ? 39.2 600 ? 34 700 ? 29.4 800 ? 26.1 900 ? 23.2 1000 ? 21 1100 ? 19.1 1200 ? 17.4 1300 ? 16.2 1400 ? 15 1500 ? over ? current ? protection ? the ? over ? current ? (oc) ? protection ? is ? performed ? by ? sensing ? current ? through ? the ? r ds(on) ? of ? the ? synchronous ? mosfet. ? this ? method ? enhances ? the ? converter?s ? efficiency, ? reduces ? cost ? by ? eliminating ? a ? current ? sense ? resistor ? and ? any ? layout ? related ? noise ? issues. ? the ? current ? limit ? is ? pre \ set ? internally ? and ? is ? compensated ? according ? to ? the ? ic ? temperature. ? so ? at ? different ? ambient ? temperature, ? the ? over \ current ? trip ? threshold ? remains ? almost ? constant. ?? over ? current ? protection ? circuit ? senses ? the ? inductor ? current ? flowing ? through ? the ? synchronous ? mosfet ? closer ? to ? the ? valley ? point. ? ocp ? circuit ? samples ? this ? current ? for ? 40nsec ? typically ? after ? the ? rising ? edge ? of ? the ? pwm ? set ? pulse ? which ? has ? a ? width ? of ? 12.5% ? of ? the ? switching ? period.the ? pwm ? pulse ? starts ? at ? the ? falling ? edge ? of ? the ? pwm ? set ? pulse. ? this ? makes ? valley ? current ? sense ? more ? robust ? as ? current ? is ? sensed ? close ? to ? the ? bottom ? of ? the ? inductor ? downward ? slope ? where ? transient ? and ? switching ? noise ? are ? lower ? and ? helps ? to ? prevent ? false ? tripping ? due ? to ? noise ? and ? transient. ? an ? oc ? condition ? is ? detected ? if ? the ? load ? current ? exceeds ? the ? threshold, ? the ? converter ? enters ? into ? hiccup ? mode. ? pgood ? will ? go ? low ? and ? the ? internal ? soft ? start ? signal ? will ? be ? pulled ? low. ? the ? converter ? goes ? into ? hiccup ? mode ? with ? a ? 20.48ms ? (typ.) ? delay ? as ? shown ? in ? figure ? 8. ? the ? convertor ? stays ? in ? this ? mode ? until ? the ? over ? load ? or ? short ? circuit ? is ? removed. ? the ? actual ? dc ? output ? current ? limit ? point ? will ? be ? greater ? than ? the ? valley ? point ? by ? an ? amount ? equal ? to ? approximately ? half ? of ? peak ? to ? peak ? inductor ? ripple ? current. ? the ? current ? limit ? point ? will ? be ? a ? function ? of ? the ? inductor ? value, ? input ? ,output ? voltage ? and ? the ? frequency ? of ? operation. ? ? ? - 20 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 20 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 (2) 2 ocp limit i ii ? ?? ? i ocp = ? dc ? current ? limit ? hiccup ? point ? i limit = ? current ? limit ? valley ? point ? i=inductor ? ripple ? current ? ? figure ? 8: ? timing ? diagram ? for ?? current ? limit ? hiccup ?? thermal ? shutdown ? temperature ? sensing ? is ? provided ? inside ? ir3895. ? the ? trip ? threshold ? is ? typically ? set ? to ? 145 o c. ? when ? trip ? threshold ? is ? exceeded, ? thermal ? shutdown ? turns ? off ? both ? mosfets ? and ? resets ? the ? internal ? soft ? start. ? automatic ? restart ? is ? initiated ? when ? the ? sensed ? temperature ? drops ? within ? the ? operating ? range. ? there ? is ?? a ? 20 o c ? hysteresis ? in ? the ? thermal ? shutdown ? threshold. ? external ? synchronization ? ir3895 ? incorporates ? an ? internal ? phase ? lock ? loop ? (pll) ? circuit ? which ? enables ? synchronization ? of ? the ? internal ? oscillator ? to ? an ? external ? clock. ? this ? function ? is ? important ? to ? avoid ? sub \ harmonic ? oscillations ? due ? to ? beat ? frequency ? for ? embedded ? systems ? when ? multiple ? point \ of \ load ? (pol) ? regulators ? are ? used. ? a ? multi \ function ? pin, ? rt/sync, ? is ? used ? to ? connect ? the ? external ? clock. ? if ? the ? external ? clock ? is ? present ? before ? the ? converter ? turns ? on, ? rt/sync ? pin ? can ? be ? connected ? to ? the ? external ? clock ? signal ? solely ? and ? no ? other ? resistor ? is ? needed. ? if ? the ? external ? clock ? is ? applied ? after ? the ? converter ? turns ? on, ? or ? the ? converter ? switching ? frequency ? needs ? to ? toggle ? between ? the ? external ? clock ? frequency ? and ? the ? internal ? free \ running ? frequency, ? an ? external ? resistor ? from ? rt/sync ? pin ? to ? gnd ? is ? required ? to ? set ? the ? free \ running ? frequency. ?? when ? an ? external ? clock ? is ? applied ? to ? rt/sync ? pin ? after ? the ? converter ? runs ? in ? steady ? state ? with ? its ? free \ running ? frequency, ? a ? transition ? from ? the ? free \ running ? frequency ? to ? the ? external ? clock ? frequency ? will ? happen. ? this ? transition ? is ? to ? gradually ? make ? the ? actual ? switching ? frequency ? equal ? to ? the ? external ? clock ? frequency, ? no ? matter ? which ? one ? is ? higher. ? on ? the ? contrary, ? when ? the ? external ? clock ? signal ? is ? removed ? from ? rt/sync ? pin, ? the ? switching ? frequency ? is ? also ? changed ? to ? free \ running ? gradually. ? in ? order ? to ? minimize ? the ? impact ? from ? these ? transitions ? to ? output ? voltage, ? a ? diode ? is ? recommended ? to ? add ? between ? the ? external ? clock ? and ? rt/sync ? pin, ? as ? shown ? in ? fig9a. ? figure ? 9b ? shows ? the ? timing ? diagram ? of ? these ? transitions. ? ir3895 rt/sync gnd figure ? 9a: ? configuration ? of ? external ? synchronization figure ? 9: ? timing ? diagram ? for ? synchronization ?? to ? the ? external ? clock ? (fs1>fs2 ? or ? fs1 - 22 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 22 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 3, ? the ? error \ amplifier ? (e/a) ? has ? been ? depicted ? with ? three ? positive ? inputs. ? ideally, ? the ? input ? with ? the ? lowest ? voltage ?? is ? used ? for ? regulating ? the ? output ? voltage ? and ? the ? other ?? two ? inputs ? are ? ignored. ? in ? practice ? the ? voltage ? of ? the ? other ? two ? inputs ? should ? be ? about ? 200mv ? greater ? than ? the ?? low \ voltage ? input ? so ? that ? their ? effects ? can ? completely ?? be ? ignored. ? vp ? is ? internally ? biased ? to ? 3.3v ? via ? a ? high ? impedance ? path. ? for ? normal ? operation, ? vp ? and ? vref ? is ?? left ? floating ? (vref ? should ? have ? a ? bypass ? capacitor). ?? therefore, ? in ? normal ? operating ? condition, ? after ? enable ? goes ? high, ? the ? internal ? soft \ start ? (intl_ss) ? ramps ? up ? the ? output ? voltage ? until ? vfb ? (voltage ? of ? feedback/fb ? pin) ? reaches ? about ? 0.5v. ? then ? vref ? takes ? over ? and ? the ? output ? voltage ? is ? regulated.. ? ? tracking \ mode ? operation ? is ? achieved ? by ? connecting ? vref ? to ? gnd. ? then, ? while ? vp=0, ? enable ? is ? taken ? above ? its ? threshold ? so ? that ? the ? soft \ start ? circuit ? generates ? intl_ss ? signal. ? after ? the ? intl_ss ? signal ? reaches ? the ? final ? value ? (refer ? to ? fig.5c) ? , ? ramping ? up ? the ? vp ? input ? will ? ramp ? up ? the ? output ? voltage. ? in ? tracking ? mode, ? vfb ? always ? follows ? vp ? which ? means ? vout ? is ? always ? proportional ? to ? vp ? voltage ? (typical ? for ? ddr/vtt ? rail ? applications). ? the ? effective ? vp ? variation ? range ? is ? 0v~1.2v. ? in ? sequencing ? mode ? of ? operation ? (simultaneous ? or ? ratiometric), ? vref ? is ? left ? floating ? and ? vp ? is ? kept ? to ? ground ? level ? until ? intl_ss ? signal ? reaches ? the ? final ? value. ? then ? vp ? is ? ramped ? up ? and ? vfb ? follows ? vp. ? when ? vp>0.5v ? the ? error \ amplifier ? switches ? to ? vref ? and ? the ? output ? voltage ? is ? regulated ? with ? vref.the ? final ? vp ? voltage ? after ? sequencing ? startup ? should ? between ? 0.7v ? ~ ? 3.3v. ? ? boot vcc/ldo fb comp gnd pgnd sw vo2 (salve) pgood pgood rt/ sync pvin vp vo1 (master) s_ctrl vin vref en r e r f r c r d 6.8 v < vin < 21 v vsns ? figure ? 12: ? application ? circuit ? for ? simultaneous ?? and ? ratiometric ? sequencing ? tracking ? and ? sequencing ? operations ? can ? be ? implemented ? to ? be ? simultaneous ? or ? ratiometric ? (refer ? to ? fig. ? 13 ? and ? 14). ? figure ? 12 ? shows ? typical ? circuit ? configuration ? for ? sequencing ? operation. ? with ? this ? power \ up ? configuration, ? the ? voltage ? at ? the ? vp ? pin ? of ? the ? slave ? reaches ? 0.5v ? before ? the ? fb ? pin ? of ? the ? master. ? if ? r e /r f ? =r c /r d , ? simultaneous ? startup ? is ? achieved. ? that ? is, ? the ? output ? voltage ? of ? the ? slave ? follows ? that ? of ? the ? master ? until ? the ? voltage ? at ? the ? vp ? pin ? of ? the ? slave ? reaches ? 0.5 ? v. ? after ? the ? voltage ? at ? the ? vp ? pin ? of ? the ? slave ? exceeds ? 0.5v, ? the ? internal ? 0.5v ? reference ? of ? the ?? slave ? dictates ? its ? output ? voltage. ? in ? reality ? the ? regulation ? gradually ? shifts ? from ? vp ? to ? internal ? vref. ? the ? circuit ? shown ? in ? fig. ? 12 ? can ? also ? be ? used ? for ? simultaneous ? or ? ratiometric ? tracking ? operation ? if ? vref ? of ? the ? slave ? is ? connected ? to ? gnd. ? table ? 2 ?? summarizes ? the ? required ? conditions ? to ? achieve ? simultaneous/ratiometric ? tracking ? or ? sequencing ? operations. ? vcc vref=0.5v 1.2v soft start (slave) enable (slave) vo1 (master) vo2 (slave) (a) vo1 (master) vo2 (slave) (b) ? figure ? 13: ? typical ? waveforms ? for ? sequencing ? mode ? of ? operation: ? (a) ? simultaneous, ? (b) ? ratiometric ?? - 23 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 23 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 vcc vref=0v (slave) 1.2v soft start (slave) enable (slave) vo1 (master) vo2 (slave) (a) vo1 (master) vo2 (slave) (b) ? figure ? 14: ? typical ? waveforms ? in ? tracking ? mode ? of ? operation: ?? (a) ? simultaneous, ? (b) ? ratiometric ?? t able ? 2: ? r equired ? c onditions ? for ? s imultaneous /r atiometric ? t racking ? and ? s equencing ? (f ig . ? 12) ? operating ?? mode ? vref ? (slave) ? vp ? required ? condition normal ?? (non \ sequencing, ? non \ tracking) ? 0.5v ? (floating) ? floating ?D? simultaneous ? sequencing ? 0.5v ? ramp ? up ? from ? 0v ? r a /r b >r e / r f =r c /r d ratiometric ? sequencing ? 0.5v ? ramp ? up ? from ? 0v ? r a /r b >r e / r f >r c /r d simultaneous ? tracking ? 0v ? ramp ? up ? from ? 0v ? r e /r f ? =r c /r d ratiometric ? tracking ? 0v ? ramp ? up ? from ? 0v ? r e /r f ? >r c /r d ? vref ?? this ? pin ? reflects ? the ? internal ? reference ? voltage ? which ? is ? used ? by ? the ? error ? amplifier ? to ? set ? the ? output ? voltage. ? in ? most ? operating ? conditions ? this ? pin ? is ? only ? connected ? to ? an ? external ? bypass ? capacitor ? and ? it ? is ? left ? floating. ? a ? 1nf ? ceramic ? capacitor ? is ? recommended ? for ? the ? bypass ? capacitor. ? to ? keep ? stand ? by ? current ? to ? minimum, ? vref ? is ? not ? allowed ? come ? up ? until ? en ? starts ? going ? high. ? in ? tracking ? mode ? this ? pin ? should ? be ? pulled ? to ? gnd. ? for ? margining ? applications, ? an ? external ? voltage ? source ? is ? connected ? to ? vref ? pin ? and ? overrides ? the ? internal ? reference ? voltage. ? the ? external ? voltage ? source ? should ? have ? a ? low ? internal ? resistance ? (<100 ) ? and ? be ? able ? to ? source ? and ? sink ? more ? than ? 25a. ? ? power ? good ? output ? (tracking, ? sequencing, ? vref ? margining) ? ir3895 ? continually ? monitors ? the ? output ? voltage ? via ? the ? sense ? pin ? (vsns) ? voltage. ? the ? vsns ? voltage ? is ? an ? input ? to ? the ? window ? comparator ? with ? upper ? and ? lower ? threshold ? of ? 0.6v ? and ? 0.45v ? respectively. ? pgood ? signal ? is ? high ? whenever ? vsns ? voltage ? is ? within ? the ? pgood ? comparator ? window ? thresholds. ? the ? pgood ? pin ? is ? open ? drain ? and ? it ? needs ? to ? be ? externally ? pulled ? high. ? high ? state ? indicates ? that ? output ? is ? in ? regulation. ?? the ? threshold ? is ? set ? differently ? at ? different ? operating ? modes ? and ? the ? results ? of ? the ? comparison ? sets ? the ? pgood ? signal. ? figures ? 15, ? 16, ? and ? 17 ? show ? the ? timing ? diagram ? of ? the ? pgood ? signal ? at ? different ? operating ? modes. ? vsns ? signal ? is ? also ? used ? by ? ovp ? comparator ? for ? detecting ? output ? over ? voltage ? condition. ? ? figure ? 15: ? non \ sequence, ? non \ tracking ? startup ?? and ? vref ? margin ? (vp ? pin ? floating) ? ? 0.3v 0 0 0 vp vsns 0.4v pgood 0.9*vp 1.2*vp 1.28ms ? figure ? 16: ? vp ? tracking ? (vref ? =0v) ? - 24 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 24 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 ? figure ? 17: ? vp ? sequence ? and ? vref ? margin ? over \ voltage ? protection ? (ovp) ? over \ voltage ? protection ? in ? ir3895 ? is ? achieved ? by ? comparing ? sense ? pin ? voltage ? vsns ? to ? a ? pre \ set ? threshold. ?? in ? non \ tracking ? mode, ? ovp ? threshold ? can ? be ? set ? at ? 1.2*vref; ? in ? tracking ? mode, ? it ? can ? be ? at ? 1.2*vp. ? when ? vsns ? exceeds ? the ? over ? voltage ? threshold, ? an ? over ? voltage ? trip ? signal ? asserts ? after ? 2us ? (typical.) ? delay. ? then ? the ? high ? side ? drive ? signal ? hdrv ? is ? turned ? off ? immediately, ? pgood ? flags ? low. ? the ? low ? side ? drive ? signal ? is ? kept ? on ? until ? the ? vsns ? voltage ? drops ? below ? the ? threshold. ? after ? that, ? hdrv ? is ? latched ? off ? until ? a ? reset ? performed ? by ? cycling ? either ? vcc ? or ? enable. ? vsns ? voltage ? is ? set ? by ? the ? voltage ? divider ? connected ? to ? the ? output ? and ? it ? can ? be ? programmed ? externally. ? figure ? 18 ? shows ? the ? timing ? diagram ? for ? ovp ? in ? non \ tracking ? mode. ?? figure ? 18: ? timing ? diagram ? for ? ovp ? in ? non \ tracking ? mode ? soft \ stop ? (s_ctrl) ? soft \ stop ? function ? can ? make ? output ? voltage ? discharge ? gradually. ? to ? enable ? this ? function, ? s_ctrl ? is ? kept ? low ? first ? when ? en ? goes ? high. ? then ? s_ctrl ? is ? pulled ? high ? to ? cross ? the ? logic ? level ? threshold ? (typical ? 2v), ? the ? internal ? soft \ start ? ramp ? is ? initiated. ? so ? vo ? follows ? intl_ss ? to ? ramp ? up ? until ? it ? reaches ? its ? steady ? state. ? in ? soft \ stop ? process, ? s_ctrl ? needs ? to ? be ? pulled ? low ? before ? en ? goes ? low. ? after ? s_ctrl ? goes ? below ? its ? threshold, ? a ? decreasing ? ramp ? is ? generated ? at ? intl_ss ? with ? the ? same ? slope ? as ? in ? soft \ start ? ramp. ? vo ? follows ? this ? ramp ? to ? discharge ? softly ? until ? shutdown ? completely. ? figure ? 19 ? shows ? the ? timing ? diagram ? of ? s_ctrl ? controlled ? soft \ start ? and ? soft \ stop. ? if ? the ? falling ? edge ? of ? enable ? signal ? asserts ? before ? s_ctrl ? falling ? edge, ? the ? converter ? is ? still ? turned ? off ? by ? enable. ? both ? gate ? drivers ? are ? turned ? off ? immediately ? and ? vo ? discharges ? to ? zero. ? figure ? 20 ? shows ? the ? timing ? diagram ?? of ? enable ? controlled ? soft \ start ? and ? soft \ stop. ? soft ? stop ? feature ? ensures ? that ? vout ? discharges ? and ? also ? regulates ? the ? current ? precisely ? to ? zero ? with ? no ? undershoot. ?? 0 0 0 intl _ss s_ctrl vout 0 enable 0.15v 0.65v 0.15v 0.65v ? figure ? 19: ? timing ? diagram ? for ? s_ctrl ? controlled ?? soft ? start/soft ? stop ? 0 0 0 intl _ss s_ctrl vout 0.15v 0 enable 1.2v 1.0v 0.65v ? figure ? 20: ? timing ? diagram ? for ? enable ? controlled ?? soft ? start/shutdown ? - 25 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 25 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 minimum ? on ? time ? considerations ? the ? minimum ? on ? time ? is ? the ? shortest ? amount ? of ? time ? for ? ctrl ? fet ? to ? be ? reliably ? turned ? on. ? this ? is ? very ? critical ? parameter ? for ? low ? duty ? cycle, ? high ? frequency ? applications. ? conventional ? approach ? limits ? the ? pulse ? width ? to ? prevent ? noise, ? jitter ? and ? pulse ? skipping. ? this ? results ? to ? lower ? closed ? loop ? bandwidth. ? ? ir ? has ? developed ? a ? proprietary ? scheme ? to ? improve ? and ? enhance ? minimum ? pulse ? width ? which ? utilizes ? the ? benefits ? of ? voltage ? mode ? control ? scheme ? with ? higher ? switching ? frequency, ? wider ? conversion ? ratio ? and ? higher ? closed ? loop ? bandwidth, ? the ? latter ? results ? in ? reduction ? of ? output ? capacitors. ? any ? design ? or ? application ? using ? ir3895 ? must ? ensure ? operation ? with ? a ? pulse ? width ? that ? is ? higher ? than ? this ? minimum ? on \ time ? and ? preferably ? higher ? than ? 60 ? ns. ?? this ? is ? necessary ? for ? the ? circuit ? to ? operate ? without ? jitter ? and ? pulse \ skipping, ? which ? can ? cause ? high ? inductor ? current ? ripple ? and ? high ? output ? voltage ? ripple. ? in (3) v out on ss v d t ff ? ? ?????????? ? ? in ? any ? application ? that ? uses ? ir3895, ? the ? following ? condition ? must ? be ? satisfied: ? (min) (min) (min) (4) (5) (6) on on out on in s out in s on tt v t vf v vf t ? ????????????????????? ? ? ??????????? ? ? ? ? ??????????? ? the ? minimum ? output ? voltage ? is ? limited ? by ? the ? reference ? voltage ? and ? hence ? v out(min) ? = ? 0.5 ? v. ? therefore, ? for ?? v out(min) ? = ? 0.5 ? v, ? v/us 33 . 8 ns 60 v 0.5 v v in (min) (min) in ? ? ? ? ? ? ? s on out s f t v f ? therefore, ? at ? the ? maximum ? recommended ? input ? voltage ? of ? 21v ? and ? minimum ? output ? voltage, ? the ? converter ? should ? be ? designed ? at ? a ? switching ? frequency ? that ? does ? not ? exceed ? 396 ? khz. ? conversely, ? for ? operation ? at ? the ? maximum ? recommended ? operating ? frequency ? (1.65 ? mhz) ? and ? minimum ? output ? voltage ? (0.5v). ? the ? input ? voltage ? (pvin) ? should ? not ? exceed ? 5.05v, ? otherwise ? pulse ? skipping ? will ? happen. ? maximum ? duty ? ratio ?? a ? certain ? off \ time ? is ? specified ? for ? ir3895. ? this ? provides ?? an ? upper ? limit ? on ? the ? operating ? duty ? ratio ? at ? any ? given ? switching ? frequency. ? the ? off \ time ? remains ? at ? a ? relatively ? fixed ? ratio ? to ? switching ? period ? in ? low ? and ? mid ? frequency ? range, ? while ? in ? high ? frequency ? range ? this ? ratio ? increases, ? thus ? the ? lower ? the ? maximum ? duty ? ratio ? at ? which ? ir3895 ? can ? operate. ? figure ? 21 ? shows ? a ? plot ? of ? the ? maximum ? duty ? ratio ? vs. ? the ? switching ? frequency ? with ? built ? in ? input ? voltage ? feed ? forward. ?? ? ? ? figure ? 21: ? maximum ? duty ? cycle ? vs. ? switching ? frequency. ? - 26 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 26 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 design ? example ? ? the ? following ? example ? is ? a ? typical ? application ? for ? ir3895. ? the ? application ? circuit ? is ? shown ? in ? fig.28. ?? = =12 v ( 10% ) =1 2 v = 16 a ripple voltage= 1%* 6% * 50% =600 khz in o o o oo s v v. i v v v load transient f ? ? ? ! for ) ? enabling ? the ? ir3895 ? as ? explained ? earlier, ? the ? precise ? threshold ? of ? the ? enable ? lends ? itself ? well ? to ? implementation ? of ? a ? uvlo ? for ? the ? bus ? voltage ? as ? shown ? in ? fig. ? 22. ? ? figure ? 22: ? using ? enable ? pin ? for ? uvlo ? implementation ? for ? a ? typical ? enable ? threshold ? of ? v en ? = ? 1.2 ? v ? 2 (min) 12 * 1.2 (7) in en r v v rr ? ? ?????????? ? ? 21 min (8) en in( ) en v rr vv ? ???????????????????? ? ? for ? v in ? (min) =9.2v, ? r 1 =49.9k ? and ? r 2 =7.5k ? ohm ? is ? a ? good ? choice. ? programming ? the ? frequency ? for ? f s ? = ? 600 ? khz, ? select ? r t ? = ? 39.2 ? k , ? using ? table ? 1. ? output ? voltage ? programming ? output ? voltage ? is ? programmed ? by ? reference ? voltage ? and ? external ? voltage ? divider. ? the ? fb ? pin ? is ? the ? inverting ? input ? of ? the ? error ? amplifier, ? which ? is ? internally ? referenced ? to ? 0.5v. ? the ? divider ? ratio ? is ? set ? to ? provide ? 0.5v ? at ? the ? fb ? pin ? when ? the ? output ? is ? at ? its ? desired ? value. ? the ? output ? voltage ? is ? defined ? by ? using ? the ? following ? equation: ? 5 6 1(9) oref r vv r ?? ? ? ? ??????????? ?? ?? ? when ? an ? external ? resistor ? divider ? is ? connected ? to ? the ? output ? as ? shown ? in ? fig. ? 23. ? 65 (10) ref oref v rr vv ?? ? ? ???????? ?? ?? ? ?? ? for ? the ? calculated ? values ? of ? r5 ? and ? r6, ? see ? feedback ? compensation ? section. ? ? figure ? 23: ? typical ? application ? of ? the ? ir3895 ?? for ? programming ? the ? output ? voltage ? bootstrap ? capacitor ? selection ? to ? drive ? the ? control ? fet, ? it ? is ? necessary ? to ? supply ? a ? gate ? voltage ? at ? least ? 4v ? greater ? than ? the ? voltage ? at ? the ? sw ? pin, ? which ? is ? connected ? to ? the ? source ? of ? the ? control ? fet. ?? this ? is ? achieved ? by ? using ? a ? bootstrap ? configuration, ? which ? comprises ? the ? internal ? bootstrap ? diode ? and ? an ? external ? bootstrap ? capacitor ? (c1). ? the ? operation ? of ? the ? circuit ? is ? as ? follows: ? when ? the ? sync ? fet ? is ? turned ? on, ? the ? capacitor ? node ? connected ? to ? sw ? is ? pulled ? down ? to ? ground. ? the ? capacitor ? charges ? towards ? v cc ? through ? the ? internal ? bootstrap ? diode ? (fig.24), ? which ? has ? a ? forward ? voltage ? drop ? v d . ? the ? voltage ? v c ? across ? the ? bootstrap ? capacitor ? c1 ? is ? approximately ? given ? as: ? (11) cccd vv v ? ? ????????????? ? when ? the ? control ? fet ? turns ? on ? in ? the ? next ? cycle, ? the ? capacitor ? node ? connected ? to ? sw ? rises ? to ? the ? bus ? voltage ? - 27 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 27 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 v in . ? however, ? if ? the ? value ? of ? c1 ? is ? appropriately ? chosen, ? the ? voltage ? v c ? across ? c1 ? remains ? approximately ? unchanged ? and ? the ? voltage ? at ? the ? boot ? pin ? becomes: ?? ? (12) boot in cc d vvvv ? ? ? ?????????? ? ? figure ? 24: ? bootstrap ? circuit ? to ? generate ? vc ? voltage ? a ? bootstrap ? capacitor ? of ? value ? 0.1uf ? is ? suitable ? for ? most ? applications. ? input ? capacitor ? selection ?? the ? ripple ? current ? generated ? during ? the ? on ? time ? of ? the ? control ? fet ? should ? be ? provided ? by ? the ? input ? capacitor. ? the ? rms ? value ? of ? this ? ripple ? is ? expressed ? by: ? (1 ) (13) rms o iidd ? ? ? ? ???????????? ? (14) o in v d v ? ????????????????????????????????????? ? where: ? d ? is ? the ? duty ? cycle ? i rms ? is ? the ? rms ? value ? of ? the ? input ? capacitor ? current. ?? io ? is ? the ? output ? current. ? for ? i o =16a ? and ? d ? = ? 0.1, ? the ? i rms ? = ? 4.8a. ? ceramic ? capacitors ? are ? recommended ? due ? to ? their ? peak ? current ? capabilities. ? they ? also ? feature ? low ? esr ? and ? esl ? at ? higher ? frequency ? which ? enables ? better ? efficiency. ?? for ? this ? application, ? it ? is ? advisable ? to ? have ? 5x10uf, ? 25v ? ceramic ? capacitors, ? c3216x5r1e106m ? from ? tdk. ? in ? addition ? to ? these, ? although ? not ? mandatory, ?? a ? 1x330uf, ? 25v ? smd ? capacitor ? eev \ fk1e331p ? from ? panasonic ? may ? also ? be ? used ? as ? a ? bulk ? capacitor ? and ? is ? recommended ? if ? the ? input ? power ? supply ? is ? not ? located ? close ? to ? the ? converter. ?? inductor ? selection ?? the ? inductor ? is ? selected ? based ? on ? output ? power, ? operating ? frequency ? and ? efficiency ? requirements. ? a ? low ? inductor ? value ? causes ? large ? ripple ? current, ? resulting ? in ? the ? smaller ? size, ? faster ? response ? to ? a ? load ? transient ? but ? poor ? efficiency ? and ? high ? output ? noise. ? generally, ? the ? selection ? of ? the ? inductor ? value ? can ? be ? reduced ? to ? the ? desired ? maximum ? ripple ? current ? in ? the ? inductor ? ( i ). ? the ? optimum ? point ? is ? usually ? found ? between ? 20% ? and ? 50% ? ripple ? of ? the ? output ? current. ? for ? the ? buck ? converter, ? the ? inductor ? value ? for ? the ? desired ? operating ? ripple ? current ? can ? be ? determined ? using ? the ? following ? relation: ? ?? 1 ; (15) * in o s o in o in s i vv l td tf v lvv vif ? ??? ??? ? ???????????? ??? ?? ? where: ? v in ? = ? maximum ? input ? voltage ? v 0 ? = ? output ? voltage ? i ? = ? inductor ? peak \ to \ peak ? ripple ? current ? f s ? = ? switching ? frequency ? t ? = ? on ? time ? for ? control ? fet ? d ? = ? duty ? cycle ? ? if ? i ?? 30%* i o , ? then ? the ? output ? inductor ? is ? calculated ? to ? be ? 0.38 h. ? select ? l =0.4 h, ? 59pr9875n, ? from ? vitec ? which ? provides ? a ? compact, ? low ? profile ? inductor ? suitable ? for ? this ? application. ? - 28 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 28 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 output ? capacitor ? selection ? the ? voltage ? ripple ? and ? transient ? requirements ? determine ? the ? output ? capacitors ? type ? and ? values. ?? the ? criteria ? is ? normally ? based ? on ? the ? value ? of ? the ? effective ? series ? resistance ? (esr). ? however ? the ? actual ? capacitance ? value ? and ? the ? equivalent ? series ? inductance ? (esl) ? are ? other ? contributing ? components. ?? these ? components ? can ? be ? described ? as: ? () () () () () () * * (16) 8* * ooesr oesl oc oesr l in o oesl l oc os vv v v viesr vv vesl l i v cf ??? ?? ?? ??? ? ?? ?? ?? ?? ??????????? ? ?? ? where: ? v 0 ? = ? output ? voltage ? ripple ? i l ? = ? inductor ? ripple ? current ? ? since ? the ? output ? capacitor ? has ? a ? major ? role ? in ? the ? overall ? performance ? of ? the ? converter ? and ? determines ? the ? result ? of ? transient ? response, ? selection ? of ? the ? capacitor ? is ? critical. ? the ? ir3895 ? can ? perform ? well ? with ?? all ? types ? of ? capacitors. ? as ? a ? rule, ? the ? capacitor ? must ? have ? low ? enough ? esr ? to ? meet ? output ? ripple ? and ? load ? transient ? requirements. ? the ? goal ? for ? this ? design ? is ? to ? meet ? the ? voltage ? ripple ? requirement ? in ? the ? smallest ? possible ? capacitor ? size. ? therefore ? it ? is ? advisable ? to ? select ? ceramic ? capacitors ?? due ? to ? their ? low ? esr ? and ? esl ? and ? small ? size. ? six ? of ? tdk ? c2012x5r0j476m ? (47uf/0805/x5r/6.3v) ? capacitors ? is ?? a ? good ? choice. ? it ? is ? also ? recommended ? to ? use ? a ? 0.1f ? ceramic ? capacitor ? at ? the ? output ? for ? high ? frequency ? filtering. ?? feedback ? compensation ? the ? ir3895 ? is ? a ? voltage ? mode ? controller. ? the ? control ? loop ?? is ? a ? single ? voltage ? feedback ? path ? including ? an ? error ? amplifier ? and ? error ? comparator. ? to ? achieve ? fast ? transient ? response ? and ? accurate ? output ? regulation, ? a ? compensation ? circuit ? is ? necessary. ? the ? goal ? of ? the ? compensation ? network ? is ? to ? close ? the ? control ? loop ? at ? high ? crossover ? frequency ? with ? phase ? margin ? greater ? than ? 45 o . ? the ? output ? lc ? filter ? introduces ? a ? double ? pole, ?\ 40db/decade ? gain ? slope ? above ? its ? corner ? resonant ? frequency, ? and ? a ? total ? phase ? lag ? of ? 180 o . ? the ? resonant ? frequency ? of ? the ? lc ? filter ? is ? expressed ? as ? follows: ? 1 (17) 2 lc oo f lc ? ? ??????????? ?? ? figure ? 25 ? shows ? gain ? and ? phase ? of ? the ? lc ? filter. ? since ? we ? already ? have ? 180 o ? phase ? shift ? from ? the ? output ? filter ? alone, ?? the ? system ? runs ? the ? risk ? of ? being ? unstable. ? phase 0 0 f lc 0 frequency f lc frequency 0 0 -180 0 0db -40db/decade -90 gain ? figure ? 25: ? gain ? and ? phase ? of ? lc ? filter ? the ? ir3895 ? uses ? a ? voltage \ type ? error ? amplifier ? with ? high \ gain ? (110db) ? and ? high \ bandwidth ? (30mhz). ? the ? output ? of ? the ? amplifier ? is ? available ? for ? dc ? gain ? control ? and ? ac ? phase ? compensation. ? the ? error ? amplifier ? can ? be ? compensated ? either ? in ? type ? ii ? or ? type ? iii ? compensation. ? type ? ii ? compensation ? is ? shown ? in ? fig. ? 26. ? this ? method ? requires ? that ? the ? output ? capacitors ? have ? enough ? esr ? to ? satisfy ? stability ? requirements. ? if ? the ? output ? capacitor?s ? esr ? generates ? a ? zero ? at ? 5khz ? to ? 50khz, ? the ? zero ? generates ? acceptable ? phase ? margin ? and ? the ? type ? ii ? compensator ? can ? be ? used. ? ? - 29 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 29 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 the ? esr ? zero ? of ? the ? output ? capacitor ? is ? expressed ? as ? follows: ? 1 (18) 2 esr o f *esr*c ? ???????????? ? v out v ref r6 r5 c pole c3 r3 ve f z f pole e/a z f frequency gain(db) h(s) db fb comp z in ? figure ? 26: ? type ? ii ? compensation ? network ?? and ? its ? asymptotic ? gain ? plot ? the ? transfer ? function ? ( v e /v out ) ? is ? given ? by: ?? 33 53 1 () (19) f e out in z vsrc hs vzsrc ? ? ? ? ? ? ????????? ? the ? (s) ? indicates ? that ? the ? transfer ? function ? varies ? as ? a ? function ? of ? frequency. ? this ? configuration ? introduces ? a ? gain ? and ? zero, ? expressed ? by: ? ?? 3 5 33 (20) 1 (21) 2* * z r hs r f rc ? ? ?????????????????? ? ????????????? ? first ? select ? the ? desired ? zero \ crossover ? frequency ? ( f o ): ? ?? o (22) and f 1/5~1/10 * oesr s ff f ????????? ?? ? use ? the ? following ? equation ? to ? calculate ? r3: ? 5 3 2 ** * (23) * osc o esr in lc vff r r vf ? ????????????? ? where: ? v in ? = ? maximum ? input ? voltage ? v osc ? = ? amplitude ? of ? the ? oscillator ? ramp ? voltage ? f o ? = ? crossover ? frequency ? f esr ? = ? zero ? frequency ? of ? the ? output ? capacitor ? f lc ? = ? resonant ? frequency ? of ? the ? output ? filter ? r 5 ? = ? feedback ? resistor ? ? to ? cancel ? one ? of ? the ? lc ? filter ? poles, ? place ? the ? zero ? before ? the ? lc ? filter ? resonant ? frequency ? pole: ? 75 % * 1 0.75* (24) 2* zlc z oo ff f lc ? ? ? ?????????????????????????????? ? use ? equation ? 21 ? to ? calculate ? c3. ? one ? more ? capacitor ? is ? sometimes ? added ? in ? parallel ? with ? c3 ? and ? r3. ? this ? introduces ? one ? more ? pole ? which ? is ? mainly ? used ? to ? suppress ? the ? switching ? noise. ? the ? additional ? pole ? is ? given ? by: ? 3 3 3 1 (25) * 2* * p pole pole f cc r cc ? ? ??????????????????????????? ? ? the ? pole ? sets ? to ? one ? half ? of ? the ? switching ? frequency ? which ? results ? in ? the ? capacitor ? c pole : ? 3 3 3 11 (26) 1 pole s s c *r *f *r *f c ? ? ? ? ?????????? ? ? for ? a ? general ? solution ? for ? unconditional ? stability ? for ? any ? type ? of ? output ? capacitors, ? and ? a ? wide ? range ? of ? esr ? values, ? a ? type ? iii ? compensation ? network ? can ? be ? used, ? as ? shown ? in ? fig. ? 27. ? - 30 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 30 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 v out v ref r6 r5 r4 c4 c2 c3 r3 ve f z 1 f z 2 f p 2 f p 3 e / a z f z in frequency gain (db) |h(s)| db fb comp ? figure ? 27: ? type ? iii ? compensation ? network ?? and ? its ? asymptotic ? gain ? plot ? again, ? the ? transfer ? function ? is ? given ? by: ? in f out e z z s h v v ? ? ? ) ( ? by ? replacing ? z in ? and ? z f , ? according ? to ? fig. ? 27, ? the ? transfer ? function ? can ? be ? expressed ? as: ? ? ? 33 4 4 5 23 52 3 3 44 23 (1 ) 1 * () ()1 (1 ) (27) sr c sc r r cc hs s rc c sr src cc ??? ?? ?? ? ?? ?? ? ?? ? ?? ?? ? ?? ?? ??????????????????????????????????????????????????????????????? ?? ? the ? compensation ? network ? has ? three ? poles ? and ? two ? zeros ? and ? they ? are ? expressed ? as ? follows: ? 1 2 44 3 32 23 3 23 0 (28) 1 (29) 2* * 11 (30) 2* * * 2* p p p f f rc f rc cc r cc ? ? ? ? ??????????????????????????????????????????????????????????? ? ?????????????????????????????????????????? ? ? ????????? ?? ?? ? ?? ? 1 33 2 445 45 1 (31) 2* * 11 (32) 2* *( ) 2* * z z f rc f crr cr ? ?? ? ????????????????????????????????????????????? ? ? ??????????? ? ? cross ? over ? frequency ? is ? expressed ? as: ? 34 1 * * * (33) 2* * in o osc o o v frc vlc ? ? based ? on ? the ? frequency ? of ? the ? zero ? generated ? by ? the ? output ? capacitor ? and ? its ? esr, ? relative ? to ? crossover ? frequency, ? the ? compensation ? type ? can ? be ? different. ? table ? 3 ? shows ? the ? compensation ? types ? for ? relative ? locations ? of ? the ? crossover ? frequency. ? t able ? 3: ? d ifferent ? types ? of ? compensators ? compensator ? type f esr ? vs ? f o ? typical ? output ? capacitor type ? ii f lc < ? f esr ? < ? f o ? < ? f s /2 ? electrolytic type ? iii f lc < ? f o ? < ? f esr ? sp ? cap, ? ceramic ? the ? higher ? the ? crossover ? frequency ? is, ? the ? potentially ? faster ? the ? load ? transient ? response ? will ? be. ? however, ? the ? crossover ? frequency ? should ? be ? low ? enough ? to ? allow ? attenuation ? of ? switching ? noise. ? typically, ? the ? control ? loop ? bandwidth ? or ? crossover ? frequency ? ( f o ) ? is ? selected ? such ? that: ? ? ? s o f f * 1/10 ~ 1/5 ? ? the ? dc ? gain ? should ? be ? large ? enough ? to ? provide ? high ?? dc \ regulation ? accuracy. ? the ? phase ? margin ? should ? be ? greater ? than ? 45 o ? for ? overall ? stability. ? for ? this ? design ? we ? have: ? v in =12v ? v o =1.2v ? v osc =1.8v ? (this ? is ? a ? function ? of ? vin, ? pls. ? see ? feed ? forward ? section) ? v ref =0.5v ? l o =0.4uh ? c o =6x47uf, ? esr 3m ? each ? it ? must ? be ? noted ? here ? that ? the ? value ? of ? the ? capacitance ? used ????????????? in ? the ? compensator ? design ? must ? be ? the ? small ? signal ? value. ?? for ? instance, ? the ? small ? signal ? capacitance ? of ? the ? 47uf ? capacitor ???? used ? in ? this ? design ? is ? 29uf ? at ? 1.2v ? dc ? bias ? and ? 600 ? khz ? frequency. ? it ? is ? this ? value ? that ? must ? be ? used ? for ? all ? computations ? related ? to ? the ? compensation. ? - 31 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 31 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 the ? small ? signal ? value ? may ? be ? obtained ? from ? the ? manufacturer?s ? datasheets, ? design ? tools ? or ? spice ? models. ? alternatively, ? they ? may ? also ? be ? inferred ? from ? measuring ? the ? power ? stage ? transfer ? function ? of ? the ? converter ? and ? measuring ? the ? double ? pole ? frequency ? f lc ? and ? using ? equation ? (17) ?? to ? compute ? the ? small ? signal ? c o . ? these ? result ? in: ? f lc =19.1 ? khz ? f esr =1.8 ? mhz ? f s /2 =300 ? khz ?? select ? crossover ? frequency ? f 0 =80 ? khz ? since ? f lc - 33 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 33 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 boot vcc/ldo_out fb comp gnd pgnd sw s_ctrl vo=1v pgood enable rt/sync vin = 5v vin vp r5 3.32k 3.32k co=6x47uf lo 0.3 uh c4 2.2nf r4 100 r3 2.49k c3 15nf c2 180pf c1 0. 1 uf c in = 6 x 10uf r t 39.2 .k r pg 49.9k ir 3895 2.2uf c vcc pvin vref 1nf cref vsns r6 r7 3.32k 3.32k r8 u1 c5 0.1uf c6 0.1uf pgood enable ? figure ? 29: ? application ? circuit ? for ? a ? 5v ? to ? 1v, ? 16a ? point ? of ? load ? converter ? ? suggested ? bill ? of ? materials ? for ? the ? application ? circuit: ? 5v ? to ? 1v ?? part reference qty value description manufacturer part number cin 1 330uf smd electrolytic f si ze 25v 20% panasonic eev-fk1e331p 6 10uf 1206, 25v, x5r, 20% tdk c3216x5r1e106m c1 c5 c6 3 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01b cref 1 1nf 0603, 25v, cog, 5% murata grm1885c1e102ja01d c4 1 2200pf 0603,50v,x7r, 10% murata grm188r71h222ka01b c2 1 180pf 0603, 50v, np0, 5% tdk c1608c0g1h181j co 6 47uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j476m cvcc 1 2.2uf 0603, 16v, x5r, 20% tdk C1608X5R1C225M c3 1 15nf 0603,50v,x7r, 10% tdk c1608x7r1h153k cvin 1 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d lo 1 0.3uh smd 11.0x7.2x7.5mm,0.29m ? vitec 59pr9874n r3 1 2.49k thick film, 0603,1/10w,1% panasonic erj-3ekf2491v r5 r6 r7 r8 4 3.32k thick film, 0603,1/10w,1% panasonic erj-3ekf3321v r4 1 100 thick film, 0603,1/10w,1% panasonic erj-3ekf1000v rt 1 39.2k thick film, 0603,1/10w,1% panasonic erj-3ekf3922v rpg 2 49.9k thick film, 0603,1/10w,1% panasonic erj-3ekf4992v u1 1 ir3895 pqfn 5x6mm ir ir3895mpbf ? ? ? - 34 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 34 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? waveforms ? pvin ? = ? 12v, ? vo ? = ? 1.2v, ? iout ? = ? 0 \ 16a, ? room ? temperature, ? no ? air ? flow ? ? ? figure ? 30: ? start ? up ? at ? 16a ? load, ?? ch 1 :vout, ? ch 2 :vin, ? ch 3 :p good ? ch 4 :enable ? ? ? ? ? ? ? ? ? ? figure ? 32: ? start ? up ? with ? pre ? bias ? voltage, ?? 0a ? load, ? ch 1 :v o ? ? figure ? 34: ? inductor ? node ? at ? 16a ? load, ? ch 1 :sw ? node ? ? figure ? 31: ? start ? up ? at ? 16a ? load, ?? ch 1 :vout, ? ch 2 :vin, ? ch 3 : ? p good , ? ch 4 : ? vcc ? ? figure ? 33: ? output ? voltage ? ripple, ?? 16a ? load, ? ch 1 :vout ? ? figure ? 35: ? short ? circuit ? recovery, ?? ch1 \ vout, ? ch4:iout ? (5a/div) ? ? - 35 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 35 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? waveforms ? vin ? = ? 12v, ? vo ? = ? 1.2v, ? iout ? = ? 0 \ 16a, ? room ? temperature, ? no ? air ? flow ?? ? ? ? ? ? ?? ? figure ? 36: ? turn ? on ? at ? no ? load ? showing ? vcc ? level ? ????? ? ch1 \ vout, ? ch2 \ vin, ? ch3 \ vcc,ch4 \ inductor ? current ???????????????????????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 37: ? turn ? on ? at ? full ? load ? showing ? vcc ? level ?? ch1 \ vout, ? ch2 \ vin,ch3 \ vcc,ch4 \ inductor ? current ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 38: ? transient ? response, ? 8a ? to ? 16a ? step ? at ? 2.5a/usec ? slew ? rate, ?? ch 1 :v out , ? ch4 \ iout ? (5a/div) ? - 36 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 36 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? waveforms ? pvin ? = ? 12v, ? vo ? = ? 1.2v, ? iout ? = ? 0 \ 16a, ? room ? temperature, ? no ? air ? flow ? ? ? figure ? 39: ? feed ? forward ? for ? vin ? change ? from ? 6.8 ? to ? 16v, ?? ch 1 :v out , ? ch 2 :v in ? ? ? ? ? ? ? ? ? ? ? ? figure ? 41: ? external ? frequency ? synchronization ? to ? 800khz ? from ? free ? running ? 600khz, ? ch 1 :v o, ? ch2:rt/sync ? voltage,ch 3 :sw ? node ? voltage ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 43: ? voltage ? margining ? using ? vref ? pin ? ?? ch 1 :vout , ? ch3:p good, ch 4 :v ref ? ? ? ? ? ? ? ? ? ? ? figure ? 40: ? start/stop ? using ? s_ctrl ? pin, ?? ch 1 :v out , ? ch 2 :enable, ? ch 3 : ? p good, ch 4 :s_ctrl ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 42: ? over ? voltage ? protection, ?? ch 1 :vout, ? ch 3 :pgood ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 44: ? voltage ? tracking ? using ? vp ? pin ??? ch 1 \ vout, ? ch3:p good ? ,ch 4 :v p ? ? ? - 37 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 37 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 typical ? operating ? waveforms ? vin ? = ? 12v, ? vo ? = ? 1.2v, ? iout ? = ? 0 \ 16a, ? room ? temperature, ? no ? air ? flow ?? ? ? figure ? 45: ? bode ? plot ? at ? 16a ? load ? shows ? a ? bandwidth ? of ? 95.2khz ? and ? phase ? margin ? of ? 54.5 ? ? figure ? 46: ? thermal ? image ? of ? the ? board ? at ? 16a ? load, ?? test ? point ? 1 ? is ? ir3895, ?? test ? point ? 2 ? is ? inductor ? ? - 38 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 38 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 layout ? recommendations ? the ? layout ? is ? very ? important ? when ? designing ? high ? frequency ? switching ? converters. ? layout ? will ? affect ? noise ? pickup ? and ? can ? cause ? a ? good ? design ? to ? perform ? with ? less ? than ? expected ? results. ? make ? the ? connections ? for ? the ? power ? components ? in ? the ? top ? layer ? with ? wide, ? copper ? filled ? areas ? or ? polygons. ? in ? general, ? it ? is ? desirable ? to ? make ? proper ? use ? of ? power ? planes ? and ? polygons ? for ? power ? distribution ? and ? heat ? dissipation. ? the ? inductor, ? output ? capacitors ? and ? the ? ir3899 ? should ? be ? as ? close ? to ? each ? other ? as ? possible. ? this ? helps ? to ? reduce ? the ? emi ? radiated ? by ? the ? power ? traces ? due ? to ? the ? high ? switching ? currents ? through ? them. ? place ? the ? input ? capacitor ? directly ? at ? the ? pvin ? pin ? of ? ir3899. ?? the ? feedback ? part ? of ? the ? system ? should ? be ? kept ? away ? from ? the ? inductor ? and ? other ? noise ? sources. ? the ? critical ? bypass ? components ? such ? as ? capacitors ? for ? vin, ? vcc ? and ? vref ? should ? be ? close ? to ? their ? respective ? pins. ? it ? is ? important ? to ? place ? the ? feedback ? components ? including ? feedback ? resistors ? and ? compensation ? components ? close ? to ? fb ? and ? comp ? pins. ? in ? a ? multilayer ? pcb ? use ? one ? layer ? as ? a ? power ? ground ? plane ? and ? have ? a ? control ? circuit ? ground ? (analog ? ground), ? to ? which ? all ? signals ? are ? referenced. ? the ? goal ? is ? to ? localize ? the ? high ? current ? path ? to ? a ? separate ? loop ? that ? does ? not ? interfere ? with ? the ? more ? sensitive ? analog ? control ? function. ? these ? two ? grounds ? must ? be ? connected ? together ? on ? the ? pc ? board ? layout ? at ? a ? single ? point. ? it ? is ? recommended ? to ? place ? all ? the ? compensation ? parts ? over ? the ? analog ? ground ? plane ? in ? top ? layer. ? the ? power ? qfn ? is ? a ? thermally ? enhanced ? package. ? based ? on ? thermal ? performance ? it ? is ? recommended ? to ? use ? at ? least ? a ? 4 \ layers ? pcb. ? to ? effectively ? remove ? heat ? from ? the ? device ? the ? exposed ? pad ? should ? be ? connected ? to ? the ? ground ? plane ? using ? vias. ? figures ? 46a \ d ? illustrates ? the ? implementation ? of ? the ? layout ? guidelines ? outlined ? above, ? on ? the ? irdc3899 ? 4 \ layer ? demo ? board. ?? ? ? ? ? ? ? ? ? ? ? ? ? ? figure ? 47a: ? irdc3895 ? demo ? board ? layout ? considerations ? ? ? top ? layer ? ? compensation parts should be placed as close as possible to the comp pin ?? ? ? resistor rt and vref decoupling cap should be placed as close as possible to their pins enough copper & minimum ground length path between input and output ? ? ? a ll bypass caps should be placed as close as possible to their connecting pins switch node - 39 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 39 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 ? ? ? ? ? ? ? ? figure ? 47b: ? irdc3895 ? demo ? board ? layout ? considerations ? ? ? bottom ? layer ? ? ? ? analog ? ground ? plane ??????? ? ???? power ? ground ? plane ???????????????????????? ? ? ? ? figure ? 47c: ? irdc3895 ? demo ? board ? layout ? considerations ? ? ? mid ? layer ? 1 ? ? ? ? ? ? ? ? ? figure ? 47d: ? irdc3895 ? demo ? board ? layout ? considerations ? ? ? mid ? layer ? 2 ? single point connection between agnd & pgnd, should be close to the supirbuck kept away from noise sources ? feedback and vsns trace routing should be kept away from noise sources - 40 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 40 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 pcb ? metal ? and ? component ? placement ? evaluations ? have ? shown ? that ? the ? best ? overall ? performance ? is ? achieved ? using ? the ? substrate/pcb ? layout ? as ? shown ? in ? following ? figures. ? pqfn ? devices ? should ? be ? placed ? to ? an ? accuracy ? of ? 0.050mm ? on ? both ? x ? and ? y ? axes. ? self \ centering ? behavior ? is ? highly ? dependent ? on ? solders ?? ? and ? processes ? and ? experiments ? should ? be ? run ? to ? confirm ? the ? limits ? of ? self \ centering ? on ? specific ? processes. ? ? for ? further ? information, ? please ? refer ? to ? ?supirbuck? ? multi \ chip ? module ? (mcm) ? power ? quad ? flat ? no \ lead ? (pqfn) ? board ? mounting ? application ? note .? ? (an1132) ? ? figure ? 48: ? pcb ? metal ? pad ? sizing ? and ? spacing ? (all ? dimensions ? in ? mm) ? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format - 41 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 41 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 solder ? resist ? ? ir ? recommends ? that ? the ? larger ? power ? or ? land ? area ? pads ? are ? solder ? mask ? defined ? (smd.) ?? this ? allows ? the ? underlying ? copper ? traces ? to ? be ? as ? large ? as ? possible, ? which ? helps ? in ? terms ? of ? current ? carrying ? capability ? and ? device ? cooling ? capability. ? ? when ? using ? smd ? pads, ? the ? underlying ? copper ? traces ? should ? be ? at ? least ? 0.05mm ? larger ? (on ? each ? edge) ? than ? the ? solder ? mask ? window, ? in ? order ? to ? accommodate ? any ? layer ? to ? layer ? misalignment. ? (i.e. ? 0.1mm ? in ? x ? & ? y.) ? ? however, ? for ? the ? smaller ? signal ? type ? leads ? around ? the ? edge ? of ? the ? device, ? ir ? recommends ? that ? these ? are ? non ? solder ? mask ? defined ? or ? copper ? defined. ? ? when ? using ? nsmd ? pads, ? the ? solder ? resist ? window ? should ? be ? larger ? than ? the ? copper ? pad ?? by ? at ? least ? 0.025mm ? on ? each ? edge, ? (i.e. ? 0.05mm ?? in ? x&y,) ? in ? order ? to ? accommodate ? any ? layer ? to ? layer ? misalignment. ? ? ensure ? that ? the ? solder ? resist ? in \ between ? the ? smaller ? signal ? lead ? areas ? are ? at ? least ? 0.15mm ? wide, ? due ? to ? the ? high ? x/y ? aspect ? ratio ? of ? the ?? solder ? mask ? strip. ?? figure ? 49: ? solder ? resist ? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format - 42 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 42 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 stencil ? design ? ? stencils ? for ? pqfn ? can ? be ? used ? with ? thicknesses ?? of ? 0.100 \ 0.250mm ? (0.004 \ 0.010"). ? stencils ? thinner ? than ? 0.100mm ? are ? unsuitable ? because ? they ? deposit ? insufficient ? solder ? paste ? to ? make ? good ? solder ? joints ? with ? the ? ground ? pad; ? high ? reductions ? sometimes ? create ? similar ? problems. ? stencils ? in ?? the ? range ? of ? 0.125mm \ 0.200mm ? (0.005 \ 0.008"), ? with ? suitable ? reductions, ? give ? the ? best ? results. ? ? ? evaluations ? have ? shown ? that ? the ? best ? overall ? performance ? is ? achieved ? using ? the ? stencil ? design ? shown ? in ? following ? figure. ? this ? design ? is ? for ?? a ? stencil ? thickness ? of ? 0.127mm ? (0.005"). ?? the ? reduction ? should ? be ? adjusted ? for ? stencils ?? of ? other ? thicknesses. ? ? ? ? figure ? 50: ? stencil ? pad ? spacing ? (all ? dimensions ? in ? mm) ? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format - 43 -p august ? 08, ? 2012 ???? | ? data ? sheet| ??? rev ? 3.1 43 ir3895 ? 16a ? highly ? integrated ? supirbuck ?? single \ input ? voltage, ? synchronous ? buck ? regulator ?? pd \ 97746 ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the consumer market visit us at www.irf.com for sales contact information data and specifications subj ect to change without notice. 12/11 figure ? 52: ? package ? dimensions dim milimiters inches dim milimiters inches min max min max min max min max a 0.800 1.000 0.0315 0.0394 l 0.350 0.450 0.0138 0.0177 a1 0.000 0.050 0.0000 0.0020 m 2.441 2.541 0.0961 0.1000 b 0.375 0.475 0.1477 0.1871 n 0.703 0.803 0.0277 0.0316 b1 0.250 0.350 0.0098 0.1379 o 2.079 2.179 0.0819 0.0858 c 0.203 ref. 0.008 ref. p 3.242 3.342 0.1276 0.1316 d 5.000 basic 1.969 basic q 1.265 1.365 0.0498 0.0537 e 6.000 basic 2.362 basic r 2.644 2.744 0.1041 0.1080 e 1.033 basic 0.0407 basic s 1.500 1.600 0.0591 0.0630 e1 0.650 basic 0.0256 basic t1, t2, t3 0.401 basic 0.016 bacis e2 0.852 basic 0.0335 basic t4 1.153 basic 0.045 basic t5 0.727 basic 0.0286 basic marking information figure ? 51: ? marking ? information |
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